As electronic devices become denser in these days, there are demands for multilayering of circuit boards such as flexible printed-wiring boards used in those devices and reduction in line widths of circuits formed on the circuit boards. Build-up methods are used as a technique for multilayering such multilayer circuit boards. In build-up methods, resin layers made only of a resin and conductor layers are stacked on top of each other and interlayer connections are provided between the individual layers.
The build-up methods can be broadly classified into two groups: methods in which via holes are formed in resin layers and then interlayer connections are provided and method in which interlayer connections are formed and then resin layers are stacked. The interlayer connections are divided into those in which via holes are formed by plating and those in which via holes are formed by a conductive paste.
As a technique capable of providing stacked vias and increasing the density and simplifying wiring design, a method has been disclosed in which fine via holes for interlayer connections are formed in a resin layer by laser and are filled with a conductive adhesive such as a copper paste, and the conductive adhesive is used to provide electrical connection (see for example Japanese Laid-Open patent publication No. 8-316598).
However, this method is not always sufficiently reliable because layers are electrically interconnected by a conductive adhesive. Furthermore, because the method requires an advanced technique for filling small via holes with a conductive adhesive, it is difficult for the method to cope with finer wiring patterns.
Therefore, instead of the method of filling via holes with a conductive adhesive, a technique that uses metal protrusions (conductive posts) has been used. For example, a method has been disclosed in which when layers are interconnected, an interlayer adhesive is physically forced out and a conductive post and a connecting pad are interconnected (see for example Japanese Laid-open patent publication No. 11-54934).
However, this method is not sufficiently reliable in some cases because it is difficult to completely remove the interlayer adhesive from between a conductive post and a connecting pad.
One method for forming a multilayer substrate having finer circuit patterns is a bonding method using bump plating. For example, the following method is used to form a multilayer substrate.
A substrate 2 including a base 202 and a conductive post 204 which is protruding from the base 202 made of copper and a metal, or copper and an alloy, and a film 5 with interlayer adhesive are prepared (FIG. 2(a)). Then, the substrate 2 including the conductive post 204 and the film 5 with interlayer adhesive are bonded together by thermocompression (FIGS. 2(b), 2(c)).
Depending on the thicknesses and types of the interlayer adhesive 104 and a protective film 106, the protrusion of the conductive post 204 cannot completely be buried with the interlayer adhesive 104 and a void 602 can occur around the conductive post 204 (FIG. 2(d)).
After the protective film 106 is peeled off (FIG. 2(e)), the void 602 is left. The interlayer adhesive is removed with the protective film 106 when the protective film 106 is peeled off and a void 602 occurs around the conductive post where there is not the interlayer adhesive (FIG. 2(f)).
Then, a substrate 3 including a base 304 provided with a land 302 for connecting with the conductive post 204 is prepared (FIG. 2(f)). The substrate 2 including the conductive post 204 and the substrate 3 including the land 302 are bonded together through the interlayer adhesive 104 to provide a multilayer substrate 6 (FIG. 2(h)).
However, the void 602 not filled with the adhesive is not completely filled with the adhesive even by heat and pressure during pressure bonding between the layers but the void between the land 302 and the conductive post 604 remains (FIGS. 2(g), 2(h)).
As shown in FIG. 3, in the case of a substrate 2 having a complicated pattern shape with conductive posts 204 or a substrate 3 with conductive pads 302 having a complicated pattern shape, or a complicated conductor circuit or a highly dense circuit, an excessive or insufficient pressure can be applied to a portion of the pattern or circuit. As a result, the interlayer adhesive 104 can be left at the top portion 206 of a conductive post 204 because the conductive post 204 cannot completely force out the interlayer adhesive 104 (FIGS. 3(d), 3(e), 3(f), 3(g)). Consequently, metal bonding cannot provide an adequate electrical connection due to the interlayer adhesive 104 remaining between the conductive post 204 and the conductive pad 302 (FIG. 3(h)). Steps shown in FIGS. 3(a) to 3(c) are the same as those in FIG. 2.
A film 25 with interlayer adhesive is bonded by thermocompression to the circuit board 3 having a conductive pad 302 that receives a conductive post (FIGS. 8(a), 8(b)). In doing this, pressure applied to the circuit can be insufficient in the case of a complicated conductor circuit or dense circuit, like a circuit board 2 having conductive posts 104. Consequently, the interlayer adhesive 124 cannot be forced out but remain on the conductive pad 302 and the surface of the conductor circuit 306.
A substrate 211 obtained in FIG. 7(f) and a substrate 311 obtained in FIG. 8(c) are set in such a manner that the surface of the adhesive faces the substrate (FIG. 9(a)) and cured by heat to obtain a multilayer substrate 23 (FIG. 9(c)). However, an adequate electrical connection cannot be provided in some cases because the interlayer adhesive 104, 124 at the top portion 106 of a conductive pad covered by the adhesive, or the adhesive on a conductor circuit surface 302, 306 cannot completely be forced out (FIG. 9(b)) but remains (FIG. 9(c)).
There is a method in which an adhesive on conductive posts and on conductor circuits is removed by polishing in order to completely remove the adhesive on the conductive post and conductor circuit (for example see Japanese Laid-open patent publication No. 2000-059028). However, this method has a technical problem that the number of man-hours is increased because the step of polishing is added, and a high precision of polishing is required.
The following method is disclosed in Japanese Laid-open patent publication No. 8-195560. A conductive post having a solder layer formed on its top is used and the conductive post is passed through an uncured resin layer and an uncured adhesive layer at a temperature lower than the melting temperature of the solder. A pressure of approximately 2.5 MPa is applied to a connecting pad and then the adhesive layer is cured. The solder is melted and then cooled to form a solder bonding.
However, when fabricating a circuit board by making interlayer connections with pressure applied in this way, a phenomenon has occurred in which a circuit in an internal layer is deformed and the circuit board is heaved due to deformation of an internal layer circuit. There are tendencies that the deformation and heaves become especially noticeable as the number of internal circuit layers increases.    Patent Document 1: Japanese Laid-open patent publication No. 8-316598    Patent Document 2: Japanese Laid-open patent publication No. 11-54934    Patent Document 3: Japanese Laid-open patent publication No. 2000-059028    Patent Document 4: Japanese Laid-open patent publication No. 8-195560